This invention relates generally to integrated circuit processes and fabrication, and more particularly to a method for transferring a multi-level photoresist pattern to an interlevel dielectric.
The demand for progressively smaller and more powerful electronic products, in turn, fuels the need for smaller geometry integrated circuits (ICs), and large substrates. It also creates a demand for a denser packaging of circuits onto IC substrates. The desire for smaller geometry IC circuits requires that the interconnections between components and dielectric layers be as small as possible. Therefore, research continues into reducing the width of via interconnects and connecting lines. Copper is a natural choice to replace aluminum in the effort to reduce the size of lines and vias in an electrical circuit. The conductivity of copper is approximately twice that of aluminum and over three times that of tungsten. As a result, the same current can be carried through a copper line having half the cross-section of an aluminum line.
The electromigration characteristics of copper are also much superior to those of aluminum. Copper is approximately ten times better than aluminum with respect to electromigration. As a result, a copper line, even one having a much smaller width than aluminum line, is able to maintain electrical and mechanical integrity.
There have been problems associated with the use of copper, however, in IC processing. Copper pollutes many of the materials used in IC processes and, therefore, care must be taken to keep copper from migrating. In addition, copper is especially prone to oxidation, especially during oxygen etch processes. Care must be taken to protect copper from exposure during etch processes, annealing, and processes requiring high temperature. Also, the oxidation products of copper are difficult to clean. In addition, copper cannot be deposited onto substrates using the conventional processes for the deposition of aluminum. That is, new deposition processes have been developed for use with copper, instead of aluminum, in the lines and interconnects of an IC interlevel dielectric.
It is impractical to sputter metal, either copper or aluminum to fill small diameter vias, it has poor gap filling capability. To deposit copper, a chemical vapor deposition (CVD) technique has been developed in the industry. However, even with the CVD technique, the convention etch process method cannot be used. The low volatility of copper etch products require copper to be removed (vaporized) at high temperatures, approximately 250.degree. C., which is too high for photoresist masks. Due to oxidation cooper cannot be removed with a plasma etch. Wet etches are isotropic, and so too imprecise for many applications. Therefore, the IC processing industry has developed a process to form a via using CVD without etching the copper. The new method is called the inlay, or damascene, process.
The damascene method for forming a via between a substrate surface and an overlying dielectric surface is described below. The underlying substrate surface is first completely covered with a dielectric, such as oxide. A patterned photoresist profile is then formed over the oxide. The resist profile has an opening, or hole, in the photoresist corresponding to the area in the oxide where the via is to be formed. Other areas of the oxide to be left in place are covered with photoresist. The photoresist covered dielectric is then etched to remove oxide underlying the hole in the photoresist. The photoresist is then stripped away. CVD copper is then used to fill the via. A layer consisting of oxide with a copper via through it now overlies the substrate surface. The excess copper remaining is removed with a chemical mechanical polish (CMP) process, as is well known in the art.
Since the damascene processing method is relatively new to the IC industry, refinements in the technique are ongoing. One refinement is the dual damascene method. In the dual damascene method vias, interconnects, and lines are formed in a dielectric at two different levels. In terms of the example of the damascene process in the preceding paragraph, the dual damascene process adds a second via, or interconnecting line, in the deposited oxide that extends from the new (oxide) surface to a level in the oxide between the underlying substrate surface and the new (oxide) surface. The dual damascene method is described in greater detail as prior art in the detailed description of the preferred embodiments and in FIGS. 1 through 6.
One known method of performing the dual damascene process is through multiple photoresist mask and etch steps. A single level photoresist profile is formed on a layer deposited dielectric and a via pattern is formed by etching to a first interlevel in the dielectric material. At this point in the process the via is only partially etched. The photoresist is then stripped and a second single layer photoresist profile is formed on the dielectric surface to form an interconnect pattern to a second interlevel in the dielectric material. Coincident with etching the interconnect, the via is etched such that interconnects in underlying substrate layers are exposed to allow electrical contact. Aligning the photoresist profiles is a problem using this method. If the two photoresist profiles are not aligned correctly, then intersecting features in the dielectric material will be misaligned. That is, a conductive line associated with the first photoresist pattern may not correctly intersect a via associated with the second photoresist profile. Alignment errors can be corrected by making the intersecting features oversized, but this takes away from the overall goal of reducing the size of connecting lines and vias. Alignment problems reduce yields, and increase cost and the complexity of IC processes.
Another known method of performing the dual damascene process uses photoresist profiles having multiple levels, or thicknesses, to form vias and interconnect at multiple levels in an IC dielectric. An electron beam or laser may be used to directly write a multi-level pattern into photoresist, but is not commercially practical. So called "gray-tone" masks, formed from repetitive patterns of dots that appear as transparent holes on the chromium mask of the reticle, have also been used to form multi-level resist profiles as described by Pierre Sixt, "Phase Masks and Gray-Tone Masks", Semiconductor FabTech, 1995, page 209. Sixt also gives a general description for a process to transfer the multi-level resist onto a dielectric. The process relies on a one-to-one etch selectivity between the dielectric material and the resist material. The dielectric and the overlying photoresist profile are then etched together so that any exposed dielectric material is etched at the same rate as overlying photoresist material. Thinner layers of resist cause a deeper etch into the dielectric so that, after etching, the dielectric shape generally resembles the photoresist pattern overlying the dielectric at the beginning of the process. One problem with this method is finding dielectric materials and photoresist materials that have identical etch selectivity. It is also difficult to transfer various features, especially small or relatively complicated features, into a dielectric using this method. Polymers and by-products of the etch process tend to collect on areas of the resist pattern, changing the shape and etch rates of the resist profile. Further, the article discloses that vias made by this method have a relatively large size, approximately 25 .mu.m, due to the resolution limits imposed with the pixel size in the gray-tone mask. Vias of this size are approximately two orders of magnitude larger than vias formed through conventional methods, and are unsuited for most IC processes.
A multi-level photoresist pattern suitable for use in the method of the present invention is disclosed in co-pending application Ser. No. 08/665,063, filed Jun. 10, 1996, entitled "Multiple Exposure Masking System For Forming Multi-Level Resist Profiles", invented by Bruce Dale Ulrich, Docket No. SMMT 234. A reticle to form a multi-level photoresist pattern suitable for use with the present invention is disclosed in co-pending application Ser. No. 08/660,820, filed Jun. 10, 1996, entitled "Multi-Level Reticle System and Method for Forming Resist Profiles", invented by David Russell Evans, Tue Nguyen, and Bruce Dale Ulrich, Docket No. SMT 166. Both, above mentioned applications are assigned to the same assignees as the instant application.
It would be advantageous to employ a method of forming vias and interconnects to at least two different interlevels beneath the surface of an IC dielectric to perform a damascene process without concern for aligning a series of photoresist masks.
It would be advantageous to use one resist profile, having a plurality of levels, to reduce the number of steps and general complexity of the dual damascene method.
It would be advantageous to use a multi-level resist profile to achieve the via widths and feature resolutions of conventional single level resist profile etching processes.
Accordingly, in an integrated circuit wafer including levels of integrated circuit material having a surface, a method has been provided of forming electrical interconnects from the surface to a plurality of interlevels in the integrated circuit material. The method comprises the step of forming a resist profile over the surface, the resist profile having a plurality of predetermined thicknesses, and the resist profile having an opening through the resist profile to reveal a predetermined surface area. The method comprising the step of removing integrated circuit material underlying the open in the resist profile, and the step of removing a predetermined portion of the resist profile to form an opening revealing a predetermined surface area. Finally, the method provides a step of removing integrated circuit material underlying the opening, whereby integrated circuit material is removed to generally reproduce the shape of the overlying resist profile.
A method has also been provided for transferring a photoresist pattern onto an integrated circuit interlevel dielectric, including an oxide layer having interlevels and a surface, the oxide layer overlying a silicon layer. The method comprising the step of forming a photoresist pattern overlying the surface, the photoresist pattern having two thicknesses with the second thickness greater than the first thickness, the photoresist having an opening through the photoresist to expose a predetermined surface area, and the photoresist having an etch selectivity different than the oxide. A method also comprising the step of etching the surface area with C.sub.2 F.sub.6 to begin a via hole in the oxide. The method comprising the step of etching the photoresist at a temperature between 10.degree. C. and -10.degree. C. to remove a layer across the photoresist greater than the first thickness, but less than the second thickness, the photoresist being etched to expose a predetermined surface area. The method also comprising the step of etching, with C.sub.3 F.sub.8, the surface area to form a trench in the oxide from the surface to a predetermined interlevel in the oxide, and further etching the via hole begun in earlier steps to form a hole through the oxide to the silicon layer, whereby the photoresist is selectively etched to form a multi-level pattern in the oxide.